Test is an important step in the manufacture of semiconductor devices. Typically performed at both the wafer and packaged-device levels, test is normally carried out with sophisticated automatic test equipment. The equipment, often called a tester, applies test signals to each device, and compares detected output signals to expected signals. Failing devices are then discarded or repaired, if possible.
When testing memory devices, or other semiconductor devices with embedded memory (such as logic or SoC devices), the tester often includes a failure analysis memory, or catchRAM. The catchRAM stores failure information in such a manner that enables a bit-image representation of the device-under-test. This conveniently allows the test engineer to visually identify failures detected in the memory device cell array.
Recently, catchRAM architectures have progressed from compact, fast and expensive SRAM-based constructions, to large but inexpensive SDRAM implementations. DRAMS are typically much slower than SRAMs on a one-to-one comparison, but when banked, provide similar performance. One proposal for a DRAM catchRAM is described in U.S. patent application Ser. No. 09/426,486, titled “High-Speed Failure Capture Apparatus and Method For ATE”, assigned to the assignee of the present invention, and expressly incorporated herein by reference.
Although conventional DRAM-based catchRAMs provide significant cost benefits without sacrificing overall performance, the additional device banks, together with the increasing capacities of the devices-under-test, generally result in the memory being overly large for practical placement near the devices-under-test (DUTs). Consequently, conventional DRAM-based catchRAMs are generally centralized in a remote location from the DUTs, such as a mainframe rack or console.
As an example of the conventional DRAM-based catchRAM architecture, FIG. 1 illustrates a conventional memory tester 10, including a main console 12 coupled to a testhead 14. The testhead is essentially a housing that surrounds and protects a plurality of sophisticated circuit boards more commonly known as channel or instrument cards 16. Each of the channel cards includes timing, data and formatting circuitry 18, 20 and 22 for interfacing the tester to a plurality of DUTs 23.
Separated from the testhead, the much larger console 12 houses a computer workstation 24 and a plurality of centralized catchRAM DRAM banks 26. The banks each comprise a plurality of SDRAM devices that are interleaved to provide improved performance and burst mode capability. A custom high-speed data link 28 couples the channel card pin electronics 16 to the catchRAM memory in the tester console for high-speed data transmission during test. The console also houses a plurality of redundancy analyzers 30 that analyze the failure data stored by the catchRAM to arrive at possible repair solutions for the failing devices. A repair station 32 disposed in the console employs the repair solution to activate redundant rows/columns in the DUTs.
In operation, the catchRAM 24 is pre-programmed into “slices”, such that a portion of the overall memory corresponds to a region of one of the DUTs 23. This may be changed from test to test, thus providing a powerful flexibility feature in terms of the catchRAM capacity. The high-speed link 28 transfers failure information from the testhead channel cards to the corresponding catchRAM “slices” in the tester console, according to the pre-programmed user instructions.
While this construction works well for its intended applications, the high speed link 28 often adds considerable cost to the tester. This is because the link is typically customized to the tester pin electronics and often unavailable as an inexpensive off-the-shelf item. Cost is a significant factor in whether a particular tester achieves widespread market acceptance. Thus, the need exists for a DRAM catchRAM without the cost of a customized high-speed link. The present invention satisfies this need.